The present invention relates to semiconductor devices, and more particularly to a method of manufacturing a semiconductor device, which can reduce interference capacitance between gates.
In a NAND flash memory fabrication method, space in which unit active regions and unit field regions are formed is reduced as the level of integration of devices is increased. As a dielectric layer (including a floating gate, a control gate and so on) is formed in a narrow active space, the distance between the gates is reduced. Accordingly, interference capacitance becomes problematic.
An equation to calculate an interference capacitance value between conductors is C=∈×A/d (where ∈ denotes the dielectric constant, A denotes the area, and d denotes the distance). From the equation, it can be seen that the smaller the distance, the larger the area, and the higher the dielectric constant, the higher the interference capacitance value C.
Furthermore, if the distance between the gates is reduced, the interference capacitance between the gates increases, so that the read speed of a device decreases.